The only true limitation to the data rates that an all-digital receiver can process is the analog-to-digital converter (A/D). Conventional CMOS digital receivers have substantially lower clock rates than the fastest commercially available analog-to-digital converters. In such a high rate system, the minimum number of samples required for digital processing (i.e., the Nyquist rate) is required to process the fastest data rate possible (i.e., the Nyquist data rate). Because CMOS hardware has lower clock rates than gallium arsenide (GaAs) hardware and therefore the fastest A/Ds, CMOS digital receivers employing traditional serial algorithms for digital communications process data rates approximately fifteen to twenty times lower than the Nyquist data rate.
With the evolution of high-speed satellite and terrestrial communications, the applications of high data rate communication systems are becoming abundant. Existing earth orbital satellites support data rates of several hundred mega-bits per second (Mbps). NASA's next generation Telecommunication and Data Relay Satellite System (TDRSS) will support data rates up to 800 Mbps. In addition, downlink data rates in excess of one giga-bits per second (Gbps) are planned in the next three years with even higher data rates to follow. Communication systems must today process faster and handle an ever rising data throughput. In addition, numerous modulation types are available and varying data rates are required, making great flexibility in receivers necessary.
Advances in GaAs have made processing rates in the gigahertz range possible. However, the widespread use of high-speed components is costly both in non-recurring engineering costs and reproduction costs. In addition GaAs VLSI requires far more power than CMOS based processors and is far less reliable. It is difficult to implement all of the functionality of a modern all-digital receiver for modern satellite communications on a single GaAs application specific integrated circuit (ASIC). A multiple ASIC solution is required due to the lower transistor density of GaAs. CMOS has much higher transistor density, far lower non-recurring engineering and reproduction costs than GaAs. In addition to being more reliable CMOS is more power efficient than GaAs, often making it more desirable for space-based applications.
The second limitation on maximum data rate in an all-digital receiver is due to the fact that the clock rates of CMOS are far lower than those of GaAs, and therefore far lower than the Nyquist data rate possible using commercially available analog-to-digital converters. Using traditional communications algorithms, the digital receiver has to process each sample at the input sampling rate. It would be desirable to develop parallel and multirate algorithms that allow all the traditional functions of a receiver to be performed within a single CMOS VLSI ASIC at the Nyquist data rate. This system-on-a-chip methodology reduces size and power requirements over a multiple ASIC solution as well as eliminates multiple expensive non-recurring engineering costs for each ASIC. This system requires that the data be processed at a rate that is fifteen to twenty times slower than the A/D rate.
Receivers are arguably the most complicated processing element (hardware or software) in a communications system. Modern digital receivers must be flexible to process many different modulation schemes, pulse shapes and data rates. Receiver complexity is directly related, although not necessarily linearly, to the complexity of the modulation type used in the system. Many modulations developed for wireless communication are complex, and are some so complicated that it is impractical to implement them in hardware. Modern modulation development is technologically ahead of hardware, both analog and digital implementations. This is particularly true of satellite communications systems operating at very high data rates.
With the rapid growth of VLSI technology coupled with the flexibility of digital signal processing algorithms, it is very desirable to implement receivers with as much digital processing as possible. In addition, an all-digital CMOS receiver has great improvements in size, reliability and greatly reduced reproduction costs over analog receivers. It should be noted that there is no such thing as an all-digital receiver, as there is always some analog processing (i.e., the analog-to-digital conversion).
The definition of an all-digital receiver is one such that the modulated data is sampled at some intermediate frequency (IF), and the receiver functions (e.g., demodulation to base-band, symbol detection (possibly matched filtering), carrier recovery, symbol timing recovery, and symbol to bit conversion) are done using exclusively digital processing. In addition, it is often desirable to have an equalizer structure that can eliminate either fixed or time-varying channel distortions using some minimum means-square error criteria. An equalizer can be an integral part of a receiver and greatly increase its performance.
As demand for information increases data rates will continue to increase. However, the usable spectrum to transmit this information is finite. More efficient use of this spectrum becomes necessary which will in turn require that more bandwidth efficient modulations be used for transmission. Some such modulations are many times more complex than those currently used in wireless systems. It is likely that previously developed but unimplemented modulations will be used and new modulations will be developed which will make more efficient use of the spectrum. Integral to the development of a very high rate wireless communications all-digital system is the use of bandwidth efficient modulation. With the increasing data rate requirements by NASA and private industry, more efficient use of spectrum is essential. Bandwidth efficiency of the wireless channel is the primary purpose for using bandwidth efficient modulations. Bandwidth efficient modulations are defined as all modulations, which are band-limited to a modulation symbol period-to-bandwidth product (BT.sub.sym) equal to 2.0. The definition of band-limited being that at least 99.9% of the spectral energy of the modulation is contained in the passband. Bandwidth efficient modulations are necessary not only to make efficient use of channel spectrum, but also to minimize the Nyquist sampling rate for digital receivers which in turn maximizes the Nyquist data rate.
The cable modem industry has lead the field in terms of modulation complexity and bandwidth efficiency. However, a wireless system, particularly a satellite communications system generally has many different obstacles to overcome than a wire-based communications system. Satellite communications systems must generally incorporate sophisticated synchronization systems for carrier recovery and symbol timing recovery which are critical parts of receiver design and operation.
High order Quadrature Amplitude Modulation (QAM) and its numerous variations are used extensively in wire based systems and many terrestrial links. It is used in satellite communications links is limited. However, because of its bandwidth efficiency and bit-error rate performance for a given power, it is extremely likely this modulation type will see frequent use in future satellite communications systems. An example of this is the ARISE mission which requires an 8 Gbps down link using only 1.5 GHz of spectrum. The 32-QAM modulation with Nyquist pulse shaping (SRRC with roll-off factor =0.25) was determined to be the most efficient known modulation for an RF link which can reasonably be implemented.
The Nyquist data rate or near Nyquist data rate receiver will be developed for in-phase/quadrature-phase (I-Q) type modulations, M-ary PSK, and M-ary QAM because they appear to be the modulations of choice for most future high rate wireless satellite communications receivers. In addition, the receiver should use single-symbol detection filtering, as opposed to systems where symbol decisions are based on processing many symbols, such as maximum likelihood sequence detection.
Currently, 8-bit A/D converters exist which operate at rates as high as three giga-samples per second. Using band-limited Quadrature-Phase Shift Keyed (QPSK) modulation with bandwidth-symbol period product equal to 2.0 (BT.sub.sym =2.0), an all-digital receiver requires a minimum of four samples per symbol. That is the symbol rate can be 3.0.times.10.sup.9 /4=750.times.10.sup.6 symbols per second. Recall that QPSK symbols represent two binary bits, the data rate of this system, the Nyquist data rate, is then 1.5.times.10.sup.9 bits per second. The fastest all-digital QPSK CMOS receiver known operates at approximately seventy Mbps, or approximately twenty times slower than the Nyquist data rate! Numerous commercially available all-digital receivers operate near this rate and lower. This is approximately the fastest rate that can be accomplished in commercially CMOS ASICs using traditional serial communication processing algorithms. Relatively small improvements in speed can be accomplished by a full custom CMOS ASIC design.
It is reasonable to assume a sixteen order (tap) finite impulse response (FIR) filter, F(z), is used for the detection filter in both in-phase and quadrature-phase channels. In this system, F(z) will also remove the double frequency term created by the non-linear operation of mixing to baseband. This system would require (16.times.2+2).times.3.times.10.sup.9 =102,000,000,000 (102.times.10.sup.9) multiplications per second just to perform the matched filtering and digital down-conversion. There is much additional processing (multipliers, adders, etc.) required to implement a "real" receiver. This example clearly illustrates that other hardware implementations to achieve this Nyquist data rate, such as field programmable gate arrays (FPGAs), Digital Signal Processors (DSPs), are not feasible. CMOS ASICs cannot process these data rates without large parallelization. All of these technologies will continue to achieve higher processing rates in the future. However, GaAs A/D rates are also going to increase making the Nyquist data rate ever higher. This cycle may never stop, but it certainly does not appear to be the case in the foreseeable future. In addition, NASA's and IPL's data rate requirements are increasing at rates even beyond GaAs A/D rates, and the associated Nyquist data rate. Data rates of two to four Gbps are predicted in the 2002-2003 time frame, and data rates as high as forty-five Gbps are predicted by 2008. It is essential that an all-digital receiver capable of Nyquist data rates be implemented in order to make these type of data rates affordable and available to NASA scientists as well as commercial operations all over the world.